A differential comparator is often used in clock acquisition circuits such as delay-locked loops (DLL) and phase locked loops (PLL) to compare the value of a voltage at a first terminal of the differential comparator to the value of a voltage at a second terminal of the differential comparator. For some applications, the signals provided at the inputs of the differential comparator are "small swing" signals that have small amplitudes relative to the supply voltage levels. For example, for CMOS circuits wherein the supply voltage VCC is equal 3.3 volts and system ground VSS is equal to zero volts, a small swing signal may have an amplitude of 0.5 volts that swings between a low of 1.5 volts and a high of 2.0 volts. A "full swing" signal swings approximately between 3.3 volts and zero volts (ground).
Clock acquisition circuits are typically used to clock the circuitry of an integrated circuit, and the differential comparator must output full swing signals to drive the integrated circuit. The differential comparator circuit must therefore provide gain to amplify the small swing input signals to a full swing output signal. For higher frequency applications, it is difficult to provide the necessary gain using prior differential comparators.